1. Technical Field
The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to a method for Fin field effect transistors having different gains.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
The push for ever increasing device densities is particularly strong in CMOS technologies, such as the in the design and fabrication of field effect transistors (FETs). FETs are used in almost all types of integrated circuit design (i.e., microprocessors, memory, etc.) Unfortunately, increased device density in CMOS FET often results in degradation of performance and/or reliability.
One type of FET that has been proposed to facilitate increased device performance is the Fin field effect transistor, often referred to as a FinFET. In a FinFET a vertical “fin” shaped structure is defined to form the body of the transistor. Gates are then formed on one or both sides of the fin. When gates are formed on both sides of the fin, the transistor is generally referred to as a double gate FinFET.
Unfortunately, several difficulties arise in the design and fabrication of FinFET transistors. For example, there has been no efficient method for creating FinFETs having different gains on the same device. Previous methods used to form multiple FinFETs have resulted in excessive device size and thus a decrease in device density. For example, one technique used to make different devices with different gains has been to change the relative dimensions of the devices. For example, the width of devices has been increased to increase the strength of a particular device. As an other example, multiple Fins have been used in one FinFET to increase the strength of the device. Unfortunately, both these techniques increase the size of the strengthened FinFET device and thus negatively effect the device density that can be achieved.
These difficulties arise in the design of specialized circuits in FET technologies. In an SRAM cell, there are typically six transistors. Two NFETs and two PFETs form the storage cell. Two more NFETs are used as pass-gate transistors to control the connection between the storage cell and the bit-lines. For cell stability, these two pass-gate NFETs must drive less current than the NFETs in the storage cell. There are two commonly known methods for varying drive strength in FETs. First, the device width can be increased to provide a “stronger” device. This would result in a significantly larger SRAM cell. The second method would be to increase the channel length to provide a “weaker” device. This would also negatively impact the cell density.
Thus, there is a need for improved device structures and methods of fabrications of FinFETs that provide for making different devices with different gain levels without overly impacting device density.